1. Field of the Invention
The present invention relates to reading data stored in a flash memory, and more particularly, to a method and a memory controller for identifying an electric charge distribution parameter of memory units of a flash memory, to read data stored in the flash memory.
2. Description of the Prior Art
Flash memories may store data through electrically erasing and writing/programming, and may be widely applied to memory cards, solid state drives (SSDs) and portable multimedia players. Since flash memories are non-volatile memories, the data stored therein is reserved without supplying power. Further, flash memories may provide fast data reading rate and good anti-shock ability. The above properties explain why flash memories are popular.
Flash memories may be divided into NOR flash memories and NAND flash memories. NAND flash memories have advantages of reduced erasing/writing time, and each memory unit of a NAND flash memory requires a smaller chip area. Hence, compared with NOR flash memories, NAND flash memories have higher storage density and lower cost for each storage bit. In general, a flash memory stores data with memory unit arrays, and may be implemented with a floating-gate transistor. Through properly controlling the number of electric charges on the floating-gate of the floating-gate transistor, each memory unit may set a threshold voltage required for the memory unit implemented by the floating-gate transistor, in order to one bit (1-bit) or multiple bits information. In this way, when there is one or multiple predetermined control gate voltages exerted on the control gate of a floating-gate transistor, the on state of the floating-gate transistor will indicate one or multiple binary digits stored in the floating-gate transistor.
However, due to some factors, the number of charges originally stored in the flash memory unit may be affected/disturbed. For example, disturbances existed in the flash memory may be generated form write/program disturbances, read disturbances and/or retention disturbances. Take a NAND flash memory having memory units each storing multiple bits information as example, a physical page corresponds to multiple logic pages, and one or multiple control gate voltages are used to perform reading operations. For example, regarding a flash memory unit arranged for storing 3 bits information, the flash memory unit has one of 8 states (i.e. electric charge levels) corresponding to different electric charge numbers (e.g., different threshold voltages). However, since the program/erase (P/E) count and/or the data retention time changes, the threshold voltage distributions of the memory units in the flash memory unit will change accordingly. Hence, the information stored in the memory units may not be correctly obtained by using the original setting of controlling the gate voltage (e.g., the threshold voltage setting) to read the information stored in the memory units.